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? semiconductor components industries, llc, 2015 august, 2015 ? rev. 7 1 publication order number: kai ? 16050/d kai-16050 4896 (h) x 3264 (v) interline ccd image sensor descriptio n the kai ? 16050 image sensor is a 16 ? megapixel ccd in an aps ? h optical format. based on the truesense 5.5 micron interline transfer ccd platform, the sensor features broad dynamic range, excellent imaging performance, and a flexible readout architecture that enables use of 1, 2, or 4 outputs for full resolution readout up to 8 frames per second. a vertical overflow drain structure suppresses image blooming and enables electronic shuttering for precise exposure control. the sensor is available with the truesense sparse color filter pattern, a technology which provides a 2x improvement in light sensitivity compared to a standard color bayer part. the sensor shares common pga pin ? out and electrical configurations with other devices based on the truesense 5.5 micron interline transfer ccd platform, allowing a single camera design to be leveraged to support multiple members of this sensor family. table 1. general specifications parameter typical value architecture interline ccd; progressive scan total number of pixels 4964 (h) x 3332 (v) number of effective pixels 4920 (h) x 3288 (v) number of active pixels 4896 (h) x 3264 (v) pixel size 5.5 m (h) x 5.5 m (v) active image size 26.93 mm (h) x 17.95 mm (v) 32.36 mm (diag.) aps ? h format aspect ratio 3:2 number of outputs 1, 2, or 4 charge capacity 20,000 electrons output sensitivity 34 v/e ? quantum efficiency pan ( ? axa, ? qxa, ? pxa) r, g, b ( ? fxa, ? qxa) r, g, b ( ? cxa, ? pxa) 43% 28%, 35%, 38% 29%, 35%, 37% read noise (f = 40 mhz) 12 electrons rms dark current photodiode vccd 2 electrons/s 140 electrons/s dark current doubling temp. photodiode vccd 7 c 9 c dynamic range 64 db charge transfer efficiency 0.999999 blooming suppression > 300 x smear estimated ? 100 db image lag < 10 electrons maximum pixel clock speed 40 mhz maximum frame rates quad output dual output single output 8 fps 4 fps 2 fps package 72 pin pga cover glass ar coated, 2 sides note: all parameters are specified at t = 40 c unless otherwise noted. www.onsemi.com figure 1. kai ? 16050 ccd image sensor features ? bayer color pattern, truesense sparse color filter pattern, and monochrome configurations ? progressive scan readout ? flexible readout architecture ? high frame rate ? high sensitivity ? low noise architecture ? excellent smear performance ? package pin reserved for device identification applications ? industrial imaging and inspection ? traffic ? security see detailed ordering and shipping information on page 2 of this data sheet. ordering information
kai ? 16050 www.onsemi.com 2 ordering information table 2. ordering information part number description marking code kai ? 16050 ? axa ? jd ? b1 monochrome, special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai ? 16050 ? axa serial number kai ? 16050 ? axa ? jd ? b2 monochrome, special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 2 kai ? 16050 ? axa ? jd ? ae monochrome, special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 16050 ? fxa ? jd ? b1 gen2 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai ? 16050 ? fxa serial number kai ? 16050 ? fxa ? jd ? b2 gen2 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 2 kai ? 16050 ? fxa ? jd ? ae gen2 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 16050 ? qxa ? jd ? b1 gen2 color (sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai ? 16050 ? qxa serial number kai ? 16050 ? qxa ? jd ? b2 gen2 color (sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 2 kai ? 16050 ? qxa ? jd ? ae gen2 color (sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade table 3. evaluation support catalog number product name description 4h2207 g2 ? fpga ? bd ? 14 ? 40 ? a ? gevk fpga board for it ? ccd evaluation hardware 4h2209 kai ? 72pin ? head ? bd ? a ? gevb 72 pin imager board for it ? ccd evaluation hardware 4h2211 lens ? mount ? kit ? b ? gevk lens mount kit for it ? ccd evaluation hardware see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com.
kai ? 16050 www.onsemi.com 3 table 4. not recommended for new designs part number description marking code kai ? 16050 ? cxa ? jd ? b1 gen1 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai ? 16050 ? cxa serial number kai ? 16050 ? cxa ? jd ? b2 gen1 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 2 kai ? 16050 ? cxa ? jd ? ae gen1 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 16050 ? pxa ? jd ? b1 gen1 color (truesense sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai ? 16050 ? pxa serial number kai ? 16050 ? pxa ? jd ? b2 gen1 color (truesense sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 2 kai ? 16050 ? pxa ? jd ? ae gen1 color (truesense sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade
kai ? 16050 www.onsemi.com 4 device description architecture figure 2. block diagram 22 dark 22 v1b 12 buffer 12 12 22 m x 5.5 m pixels 2448 2448 2448 2448 (last vccd phase = v1 h1s) v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2bc h2sla oga h2slc ogc h2sld ogd h2slb ogb esd esd sub sub 8 22 10 1 12 8 22 10 1 12 8 22 10 1 12 8 22 12 22 devid 10 1 fdgab fdgab fdgcd fdgcd 12 dark reference pixels there are 22 dark reference rows at the top and 22 dark rows at the bottom of the image sensor. the dark rows are not entirely dark and so should not be used for a dark reference level. use the 22 dark columns on the left or right side of the image sensor as a dark reference. under normal circumstances use only the center 20 columns of the 22 column dark reference due to potential light leakage. dummy pixels within each horizontal shift register there are 11 leading additional shift phases. these pixels are designated as dummy pixels and should not be used to determine a dark reference level. in addition, there is one dummy row of pixels at the top and bottom of the image. active buffer pixels 12 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. these pixels are light sensitive but are not tested for defects and non ? uniformities. image acquisitio n an electronic representation of an image is formed when incident photons falling on the sensor plane create electron ? hole pairs within the individual silicon photodiodes. these photoelectrons are collected locally by the formation of potential wells at each photosite. below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non ? linearly dependent on wavelength. when the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming.
kai ? 16050 www.onsemi.com 5 esd protection adherence to the power ? up and power ? down sequence is critical. failure to follow the proper power ? up and power ? down sequences may cause damage to the sensor. see power ? up and power ? down sequence section. bayer color filter pattern figure 3. bayer color filter pattern 22 dark 22 v1b 12 buffer 12 12 b g g r 22 fld fld 4896h x 3264v 2448 2448 2448 2448 v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2sla oga h2slc ogc h2sld ogd h2slb ogb esd esd sub sub 8 22 10 1 12 8 22 10 1 12 8 22 10 1 12 8 22 10 1 12 22 12 devid fdgab fdgab h2bc fdgcd fdgcd b g g r b g g r b g g r (last vccd phase = v1 h1s) 5.5 m x 5.5 m pixels truesense sparse color filter pattern figure 4. truesense sparse color filter pattern 22 dark 22 v1b 12 buffer 12 12 22 fld fld 4896h x 3264v 2448 2448 2448 2448 v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2sla oga h2slc ogc h2sld ogd h2slb ogb esd esd sub sub 8 22 10 1 12 8 22 10 1 12 8 22 10 1 12 8 22 10 1 12 22 12 devid fdgab fdgab h2bc fdgcd fdgcd p b g r p b p p g g g p p p r p p b g r p b p p g g g p p p r p p b g r p b p p g g g p p p r p p b g r p b p p g g g p p p r p 5.5 m x 5.5 m pixels (last vccd phase = v1 h1s)
kai ? 16050 www.onsemi.com 6 physical description pin description and device orientation figure 5. package pin designations ? top view 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 v3b pixel (1,1) v3b v1b v1b vdda vddb gnd ra gnd rb h2sla h2slb h1ba h1bb h2sa h2sb sub n/c v3t v3t v1t v1t vddc vddd gnd rc gnd rd h2slc h2sld h1bc h1bd h2sc h2sd n/c sub v4b esd v4b v2b v2b vouta voutb rda rdb oga ogb h2ba h2bb h1sa h1sb fdgab fdgab v4t devid v4t v2t v2t voutc voutd rdc rdd ogc ogd h2bc h2bd h1sc h1sd fdgcd fdgcd esd
kai ? 16050 www.onsemi.com 7 table 5. pin description pin name description 1 v3b vertical ccd clock, phase 3, bottom 3 v1b vertical ccd clock, phase 1, bottom 4 v4b vertical ccd clock, phase 4, bottom 5 vdda output amplifier supply, quadrant a 6 v2b vertical ccd clock, phase 2, bottom 7 gnd ground 8 vouta video output, quadrant a 9 ra reset gate, quadrant a 10 rda reset drain, quadrant a 11 h2sla horizontal ccd clock, phase 2, storage, last phase, quadrant a 12 oga output gate, quadrant a 13 h1ba horizontal ccd clock, phase 1, barrier, quadrant a 14 h2ba horizontal ccd clock, phase 2, barrier, quadrant a 15 h2sa horizontal ccd clock, phase 2, storage, quadrant a 16 h1sa horizontal ccd clock, phase 1, storage, quadrant a 17 sub substrate 18 fdgab fast line dump gate, bottom 19 n/c no connect 20 fdgab fast line dump gate, bottom 21 h2sb horizontal ccd clock, phase 2, storage, quadrant b 22 h1sb horizontal ccd clock, phase 1, storage, quadrant b 23 h1bb horizontal ccd clock, phase 1, barrier, quadrant b 24 h2bb horizontal ccd clock, phase 2, barrier, quadrant b 25 h2slb horizontal ccd clock, phase 2, storage, last phase, quadrant b 26 ogb output gate, quadrant b 27 rb reset gate, quadrant b 28 rdb reset drain, quadrant b 29 gnd ground 30 voutb video output, quadrant b 31 vddb output amplifier supply, quadrant b 32 v2b vertical ccd clock, phase 2, bottom 33 v1b vertical ccd clock, phase 1, bottom 34 v4b vertical ccd clock, phase 4, bottom 35 v3b vertical ccd clock, phase 3, bottom 36 esd esd protection disable pin name description 72 esd esd protection disable 71 v3t vertical ccd clock, phase 3, top 70 v4t vertical ccd clock, phase 4, top 69 v1t vertical ccd clock, phase 1, top 68 v2t vertical ccd clock, phase 2, top 67 vddc output amplifier supply, quadrant c 66 voutc video output, quadrant c 65 gnd ground 64 rdc reset drain, quadrant c 63 rc reset gate, quadrant c 62 ogc output gate, quadrant c 61 h2slc horizontal ccd clock, phase 2, storage, last phase, quadrant c 60 h2bc horizontal ccd clock, phase 2, barrier, quadrant c 59 h1bc horizontal ccd clock, phase 1, barrier, quadrant c 58 h1sc horizontal ccd clock, phase 1, storage, quadrant c 57 h2sc horizontal ccd clock, phase 2, storage, quadrant c 56 fdgcd fast line dump gate, top 55 n/c no connect 54 fdgcd fast line dump gate, top 53 sub substrate 52 h1sd horizontal ccd clock, phase 1, storage, quadrant d 51 h2sd horizontal ccd clock, phase 2, storage, quadrant d 50 h2bd horizontal ccd clock, phase 2, barrier, quadrant d 49 h1bd horizontal ccd clock, phase 1, barrier, quadrant d 48 ogd output gate, quadrant d 47 h2sld horizontal ccd clock, phase 2, storage, last phase, quadrant d 46 rdd reset drain, quadrant d 45 rd reset gate, quadrant d 44 voutd video output, quadrant d 43 gnd ground 42 v2t vertical ccd clock, phase 2, top 41 vddd output amplifier supply, quadrant d 40 v4t vertical ccd clock, phase 4, top 39 v1t vertical ccd clock, phase 1, top 38 devid device identification 37 v3t vertical ccd clock, phase 3, top 1. liked named pins are internally connected and should have a common drive signal. 2. n/c pins (19, 55) should be left floating.
kai ? 16050 www.onsemi.com 8 imaging performance table 6. typical operation conditions unless otherwise noted, the imaging performance specifications are measured using the following conditions. description condition notes light source continuous red, green and blue led illumination for monochrome sensor, only green led used. operation nominal operating voltages and timing table 7. specifications all configurations description symbol min. nom. max. units sampling plan temperature tested at ( c) notes dark field global non ? uniformity dsnu ? ? 5 mvpp die 27, 40 bright field global non ? uniformity ? 2 5 %rms die 27, 40 1 bright field global peak to peak non ? uniformity prnu ? 10 30 %pp die 27, 40 1 bright field center non ? uniformity ? 1 2 %rms die 27, 40 1 maximum photoresponse nonlinearity nl ? 2 ? % design 2 maximum gain difference between outputs g ? 10 ? % design 2 maximum signal error due to nonlinearity differences nl ? 1 ? % design 2 horizontal ccd charge capacity hne ? 50 ? ke ? design vertical ccd charge capacity vne ? 45 ? ke ? design photodiode charge capacity pne ? 20 ? ke ? die 27, 40 3 horizontal ccd charge transfer efficiency hcte 0.999995 0.999999 ? die vertical ccd charge transfer efficiency vcte 0.999995 0.999999 ? die photodiode dark current ipd ? 7 70 e/p/s die 40 vertical ccd dark current ivd ? 140 400 e/p/s die 40 image lag lag ? ? 10 e ? design antiblooming factor xab 300 ? ? design vertical smear smr ? ? 100 ? db design read noise n e ? t ? 12 ? e ? rms design 4 dynamic range dr ? 64 ? db design 4, 5 output amplifier dc offset v odc ? 9.4 ? v die 27, 40 output amplifier bandwidth f ? 3db ? 250 ? mhz die 6 output amplifier impedance r out ? 127 ? die 27, 40 output amplifier sensitivity v/ n ? 34 ? v/e ? design 1. per color 2. value is over the range of 10% to 90% of photodiode saturation. 3. the operating value of the substrate voltage, vab, will be marked on the shipping container for each device. the value of vab is set such that the photodiode charge capacity is 680 mv. 4. at 40 mhz 5. uses 20log (pne/ n e ? t ) 6. assumes 5 pf load.
kai ? 16050 www.onsemi.com 9 table 8. kai ? 16050 ? axa, kai ? 16050 ? qxa, and kai ? 16050 ? pxa 1 configurations description symbol min. nom. max. units sampling plan temperature tested at ( c) notes peak quantum efficiency qe max ? 43 ? % design peak quantum efficiency wavelength qe ? 470 ? nm design 1. this color filter set configuration (gen1) is not recommended for new designs. table 9. kai ? 16050 ? fba and kai ? 16050 ? qba gen2 color configurations with mar glass description symbol min. nom. max. units sampling plan temperature tested at ( c) notes peak quantum efficiency blue green red qe max ? 37 35 29 ? % design peak quantum efficiency wavelength blue green red qe ? 460 530 605 ? nm design table 10. kai ? 16050 ? cba and kai ? 16050 ? pba gen1 color configurations with mar glass description symbol min. nom. max. units sampling plan temperature tested at ( c) notes peak quantum efficiency blue green red qe max ? 38 35 28 ? % design 1 peak quantum efficiency wavelength blue green red qe ? 470 540 620 ? nm design 1 1. this color filter set configuration (gen1) is not recommended for new designs.
kai ? 16050 www.onsemi.com 10 typical performance curves quantum efficiency monochrome with microlens figure 6. monochrome with microlens quantum efficiency
kai ? 16050 www.onsemi.com 11 color (bayer rgb) with microlens and mar cover glass (gen2 and gen1 cfa) figure 7. color (bayer) with microlens quantum efficiency color (truesense sparse cfa) with microlens (gen2 and gen1 cfa) figure 8. color (truesense sparse cfa) with microlens quantum efficiency
kai ? 16050 www.onsemi.com 12 angular quantum efficiency for the curves marked ?horizontal?, the incident light angle is varied in a plane parallel to the hccd. for the curves marked ?vertical?, the incident light angle is varied in a plane parallel to the vccd. monochrome with microlens figure 9. monochrome with microlens angular quantum efficiency 0 10 20 30 40 50 60 70 80 90 100 ? 40 ? 30 ? 20 ? 100 10203040 relative quantum efficiency (%) angle (degrees) vertical horizontal dark current versus temperature figure 10. dark current versus temperature 0.1 1 10 100 1000 10000 2.9 3.0 3.1 3.2 3.3 3.4 1000/t (k) t (c) vccd photodiode 60 50 40 30 21 72 dark current (e/s)
kai ? 16050 www.onsemi.com 13 power ? estimated figure 11. power 0.0 0.5 1.0 1.5 2.0 2.5 10 15 20 25 30 35 40 single dual quad power (w) hccd frequency (mhz) frame rates figure 12. frame rates 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 10 15 20 25 30 35 40 single dual (left/right) quad frame rate (fps) hccd frequency (mhz)
kai ? 16050 www.onsemi.com 14 defect definitions table 11. operation conditions for defect testing at 40 c description condition notes operational mode two outputs, using vouta and voutc, continuous readout hccd clock frequency 10 mhz pixels per line 5120 1 lines per frame 1760 2 line time 547.7 sec frame time 964.0 msec photodiode integration time (pd_tint) mode a: pd_tint = frame time = 964.0 msec, no electronic shutter used vccd integration time 912.5 msec 3 temperature 40 c light source continuous red, green and blue led illumination 4 operation nominal operating voltages and timing 1. horizontal overclocking used. 2. vertical overclocking used. 3. vccd integration time = 1666 lines x line time, which is the total time a pixel will spend in the vccd registers. 4. for monochrome sensor, only the green led is used. table 12. defect definitions for testing at 40 c description definition grade 1 grade 2 mono grade 2 color notes major dark field defective bright pixel pd_tint = mode a defect 328 mv 150 300 300 1 major bright field defective dark pixel defect 12% minor dark field defective bright pixel pd_tint = mode a defect 164 mv 1500 3000 3000 cluster defect a group of 2 to 19 contiguous major defective pixels, but no more than 3 adjacent defects horizontally. 20 n/a n/a 2 cluster defect a group of 2 to 38 contiguous major defective pixels, but no more than 5 adjacent defects horizontally. n/a 30 30 column defect a group of more than 10 contiguous major defective pixels along a single column 0 4 15 2 1. for the color devices (kai ? 16050 ? cxa and kai ? 16050 ? pxa), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects ).
kai ? 16050 www.onsemi.com 15 table 13. operation conditions for defect testing at 27 c description condition notes operational mode two outputs, using vouta and voutc, continuous readout hccd clock frequency 10 mhz pixels per line 5120 1 lines per frame 3424 2 line time 547.7 sec frame time 1875.4 msec photodiode integration time (pd_tint) mode a: pd_tint = frame time = 1875.4 msec, no electronic shutter used vccd integration time 912.5 msec 3 temperature 27 c light source continuous red, green and blue led illumination 4 operation nominal operating voltages and timing 1. horizontal overclocking used. 2. vertical overclocking used. 3. vccd integration time = 1666 lines x line time, which is the total time a pixel will spend in the vccd registers. 4. for monochrome sensor, only the green led is used. table 14. defect definitions for testing at 27 c description definition grade 1 grade 2 mono grade 2 color notes major dark field defective bright pixel pd_tint = mode a defect 200 mv 150 300 300 1 major bright field defective dark pixel defect 12% cluster defect a group of 2 to 19 contiguous major defective pixels, but no more than 3 adjacent defects horizontally. 20 n/a n/a 2 cluster defect a group of 2 to 38 contiguous major defective pixels, but no more than 5 adjacent defects horizontally. n/a 30 30 column defect a group of more than 10 contiguous major defective pixels along a single column 0 4 15 2 1. for the color devices (kai ? 16050 ? cxa and kai ? 16050 ? pxa), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects ). defect map the defect map supplied with each sensor is based upon testing at an ambient (27 c) temperature. minor point defects are not included in the defect map. all defective pixels are reference to pixel 1, 1 in the defect maps. see figure 13: regions of interest for the location of pixel 1,1.
kai ? 16050 www.onsemi.com 16 test definitions test regions of interest image area roi: pixel (1, 1) to pixel (4920, 3288) active area roi: pixel (13, 13) to pixel (4908, 3276) center roi: pixel (2411, 1595) to pixel (2510, 1694) only the active area roi pixels are used for performance and defect tests. overclocking the test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. see figure 13 for a pictorial representation of the regions of interest. figure 13. regions of interest horizontal overclock 12 buffer rows 12 buffer rows 12 buffer columns 12 buffer columns 22 dark columns 22 dark columns 12 dark rows vouta 12 dark rows 4896 x 3264 active pixels 1, 1 13, 13 pixel pixel voutc
kai ? 16050 www.onsemi.com 17 tests dark field global non ? uniformity this test is performed under dark field conditions. the sensor is partitioned into 864 sub regions of interest, each of which is 136 by 136 pixels in size. the average signal level of each of the 864 sub regions of interest is calculated. the signal level of each of the sub regions of interest is calculated using the following formula: signal of roi[i] = (roi average in counts ? horizontal overclock average in counts) * mv per count where i = 1 to 864. during this calculation on the 864 sub regions of interest, the maximum and minimum signal levels are found. the dark field global uniformity is then calculated as the maximum signal found minus the minimum signal level found. units: mvpp (millivolts peak to peak) global non ? uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mv. global non ? uniformity is defined as globalnon ? uniformity 100 activeareastandarddeviation activeareasignal units: %rms. active area signal = active area average ? dark column average global p eak to peak non ? uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mv. the sensor is partitioned into 864 sub regions of interest, each of which is 136 by 136 pixels in size. the average signal level of each of the 864 sub regions of interest (roi) is calculated. the signal level of each of the sub regions of interest is calculated using the following formula: signal of roi[i] = (roi average in counts ? horizontal overclock average in counts) * mv per count where i = 1 to 864. during this calculation on the 864 sub regions of interest, the maximum and minimum signal levels are found. the global peak to peak uniformity is then calculated as: globaluniformity 100 maximumsignal minimumsignal activeareasignal units: %pp center non ? uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mv. defects are excluded for the calculation of this test. this test is performed on the center 100 by 100 pixels of the sensor. center uniformity is defined as: center roi uniformity 100 center roi standard deviation center roi signal units: %rms. center roi signal = center roi average ? dark column average dark field defect test this test is performed under dark field conditions. the sensor is partitioned into 864 sub regions of interest, each of which is 136 by 136 pixels in size. in each region of interest, the median value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the ?defect definitions? section. bright field defect test this test is performed with the imager illuminated to a level such that the output is at approximately 476 mv. prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mv. the average signal level of all active pixels is found. the bright and dark thresholds are set as: dark defect threshold = active area signal * threshold bright defect threshold = active area signal * threshold the sensor is then partitioned into 864 sub regions of interest, each of which is 136 by 136 pixels in size. in each region of interest, the average value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified.
kai ? 16050 www.onsemi.com 18 example for major bright field defective pixels: ? average value of all active pixels is found to be 476 mv ? dark defect threshold: 476 mv * 12 % = 57 mv ? region of interest #1 selected. this region of interest is pixels 13, 13 to pixels 148, 148. ? median of this region of interest is found to be 470 mv. ? any pixel in this region of interest that is (470 ? 57 mv) 413 mv in intensity will be marked defective. ? all remaining 836 sub regions of interest are analyzed for defective pixels in the same manner.
kai ? 16050 www.onsemi.com 19 operation table 15. absolute maximum ratings description symbol minimum maximum units notes operating temperature t op ? 50 +70 c 1 humidity rh +5 +90 % 2 output bias current i out 60 ma 3 off ? chip load c l 10 pf stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. noise performance will degrade at higher temperatures. 2. t = 25 c. excessive humidity will degrade mttf. 3. total for all outputs. maximum current is ? 15 ma for each output. avoid shorting output pins to ground or any low impedance source during operation. amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivi ty). table 16. absolute maximum voltage ratings between pins and ground description minimum maximum units notes vdd , vout ? 0.4 17.5 v 1 rd ? 0.4 15.5 v 1 v1b, v1t esd ? 0.4 esd + 24.0 v v2b, v2t, v3b, v3t, v4b, v4t esd ? 0.4 esd + 14.0 v fdgab, fdgcd esd ? 0.4 esd + 15.0 v h1s , h1b , h2s , h2b , h2sl , r , og esd ? 0.4 esd + 14.0 v 1 esd ? 10.0 0.0 v sub ? 0.4 40.0 v 2 1. denotes a, b, c or d 2. refer to application note using interline ccd image sensors in high intensity visible lighting conditions. power ? up and power ? down sequence adherence to the power ? up and power ? down sequence is critical. failure to follow the proper power ? up and power ? down sequences may cause damage to the sensor. figure 14. power ? up and power ? down sequence vdd sub esd vccd low hccd low time v+ v ? activate all other biases when esd is stable and sub is above 3v do not pulse the electronic shutter until esd is stable notes: 1. activate all other biases when esd is stable and sub is above 3 v 2. do not pulse the electronic shutter until esd is stable 3. vdd cannot be +15 v when sub is 0 v 4. the image sensor can be protected from an accidental improper esd voltage by current limiting the sub current to less than 10 ma. sub and vdd must always be greater than gnd. esd must always be less than gnd. placing diodes between sub, vdd, esd and ground will protect
kai ? 16050 www.onsemi.com 20 the sensor from accidental overshoots of sub, vdd and esd during power on and power off. see the figure below. the vccd clock waveform must not have a negative overshoot more than 0.4 v below the esd voltage. figure 15. all vccd clocks absolute maximum overshoot of 0.4 v 0.0v esd esd ? 0.4v example of external diode protection for sub, vdd and esd. denotes a, b, c or d figure 16. gnd sub vdd esd table 17. dc bias operating conditions description pins symbol minimum nominal maximum units maximum dc current notes reset drain rd rd +11.8 +12.0 +12.2 v 10 a 1 output gate og og ? 2.2 ? 2.0 ? 1.8 v 10 a 1 output amplifier supply vdd vdd +14.5 +15.0 +15.5 v 11.0 ma 1,2 ground gnd gnd 0.0 0.0 0.0 v ? 1.0 ma substrate sub vsub +5.0 vab vdd v 50 a 3, 8 esd protection disable esd esd ? 9.5 ? 9.0 vx_l v 50 a 6, 7, 9 output bias current vout iout ? 3.0 ? 7.0 ? 10.0 ma 1, 4, 5 1. denotes a, b, c or d 2. the maximum dc current is for one output. idd = iout + iss. see figure 17. 3. the operating value of the substrate voltage, vab, will be marked on the shipping container for each device. the value of vab is set such that the photodiode charge capacity is the nominal pne (see specifications). 4. an output load sink must be applied to each vout pin to activate each output amplifier. 5. nominal value required for 40 mhz operation per output. may be reduced for slower data rates and lower noise. 6. adherence to the power ? up and power ? down sequence is critical. see power ? up and power ? down sequence section. 7. esd maximum value must be less than or equal to v1_l + 0.4 v and v2_l + 0.4 v 8. refer to application note using interline ccd image sensors in high intensity visible lighting conditions 9. where vx_l is the level set for v1_l, v2_l, v3_l, or v4_l in the application.
kai ? 16050 www.onsemi.com 21 figure 17. output amplifier floating diffusion source follower #1 source follower #2 source follower #3 iout idd iss hccd r rd vdd og vout
kai ? 16050 www.onsemi.com 22 ac operating conditions table 18. clock levels description pins 1 symbol level minimum nominal maximum units capacitance 2 vertical ccd clock, phase 1 v1b, v1t v1_l low ? 8.2 ? 8.0 ? 7.8 v 180 nf (6) v1_m mid ? 0.2 0.0 +0.2 v1_h high +11.5 +12.0 +12.5 vertical ccd clock, phase 2 v2b, v2t v2_l low ? 8.2 ? 8.0 ? 7.8 v 180 nf (6) v2_h high ? 0.2 0.0 +0.2 vertical ccd clock, phase 3 v3b, v3t v3_l low ? 8.2 ? 8.0 ? 7.8 v 180 nf (6) v3_h high ? 0.2 0.0 +0.2 vertical ccd clock, phase 4 v4b, v4t v4_l low ? 8.2 ? 8.0 ? 7.8 v 180 nf (6) v4_h high ? 0.2 0.0 +0.2 horizontal ccd clock, phase 1 storage h1s h1s_l low ? 5.2 (7) ? 4.0 ? 3.8 v 600 pf (6) h1s_a amplitude +3.8 +4.0 +5.2 (7) horizontal ccd clock, phase 1 barrier h1b h1b_l low ? 5.2 (7) ? 4.0 ? 3.8 v 400 pf (6) h1b_a amplitude +3.8 +4.0 +5.2 (7) horizontal ccd clock, phase 2 storage h2s h2s_l low ? 5.2 (7) ? 4.0 ? 3.8 v 580 pf (6) h2s_a amplitude +3.8 +4.0 +5.2 (7) horizontal ccd clock, phase 2 barrier h2b h2b_l low ? 5.2 (7) ? 4.0 ? 3.8 v 400 pf (6) h2b_a amplitude +3.8 +4.0 +5.2 (7) horizontal ccd clock, last phase 3 h2sl h2sl_l low ? 5.2 ? 5.0 ? 4.8 v 20 pf (6) h2sl_a amplitude +4.8 +5.0 +5.2 reset gate r r_l 4 low ? 3.5 ? 2.0 ? 1.5 v 16 pf (6) r_h high +2.5 +3.0 +4.0 electronic shutter 5 sub ves high +29.0 +30.0 +40.0 v 12 nf (6) fast line dump gate fdg fdg_l low ? 8.2 ? 8.0 ? 7.8 v 50 pf (6) fdg_h high +4.5 +5.0 +5.5 1. denotes a, b, c or d 2. capacitance is total for all like named pins 3. use separate clock driver for improved speed performance. 4. reset low should be set to ?3 volts for signal levels greater than 40,000 electrons. 5. refer to application note using interline ccd image sensors in high intensity visible lighting conditions 6. capacitance values are estimated 7. if the minimum horizontal clock low level is used (?5.2 v), then the maximum horizontal clock amplitude should be used (5.2 v amplitude) to create a ?5.2 v to 0.0 v clock. if a 5 v clock driver is used, the horizontal low level should be set to ?5.0 v and the high level should be a set to 0.0 v. the figure below shows the dc bias (vsub) and ac clock (ves) applied to the sub pin. both the dc bias and ac clock are referenced to ground. figure 18. vsub ves gnd gnd
kai ? 16050 www.onsemi.com 23 device identification the device identification pin (devid) may be used to determine which on semiconductor 5.5 micron pixel interline ccd sensor is being used. table 19. device identification description pins symbol minimum nominal maximum units maximum dc current notes device identification devid devid 144,000 180,000 216,000 50 a 1, 2, 3 1. nominal value subject to verification and/or change during release of preliminary specifications. 2. if the device identification is not used, it may be left disconnected. 3. after device identification resistance has been read during camera initialization, it is recommended that the circuit be disa bled to prevent localized heating of the sensor due to current flow through the r_deviceid resistor. recommended circuit note that v1 must be a different value than v2. figure 19. device identification recommended circuit adc r_external v1 v2 devid gnd kai ? 16050 r_deviceid
kai ? 16050 www.onsemi.com 24 timing table 20. requirements and characteristics description symbol minimum nominal maximum units notes photodiode transfer t pd 3 ? ? s vccd leading pedestal t 3p 4 ? ? s vccd trailing pedestal t 3d 4 ? ? s vccd transfer delay t d 4 ? ? s vccd transfer t v 4 ? ? s vccd clock cross ? over v vcr 75 100 % 1 vccd rise, fall times t vr , t vf 5 ? 10 % 1, 2 fdg delay t fdg 2 ? ? s hccd delay t hs 1 ? ? s hccd transfer t e 25.0 ? ? ns shutter transfer t sub 1 ? ? s shutter delay t hd 1 ? ? s reset pulse t r 2.5 ? ? ns reset ? video delay t rv ? 2.2 ? ns h2sl ? video delay t hv ? 3.1 ? ns line time t line 69.3 ? ? s dual hccd readout 131.4 ? ? single hccd readout frame time t frame 115.5 ? ? ms quad hccd readout 231.1 ? ? dual hccd readout 437.8 ? ? single hccd readout 1. refer to figure 25: vccd clock rise time, fall time and edge alignment 2. relative to the pulse width 3. refer to timing diagrams as shown in figures 21, 22, 23, 24 and 25.
kai ? 16050 www.onsemi.com 25 timing diagrams the timing sequence for the clocked device pins may be represented as one of seven patterns (p1 ? p7) as shown in the table below. the patterns are defined in figure 21 and figure 22. contact on semiconductor imaging application engineering for other readout modes. table 21. device pin quad readout dual readout vouta, voutb dual readout vouta, voutc single readout vouta v1t p1t p1b p1t p1b v2t p2t p4b p2t p4b v3t p3t p3b p3t p3b v4t p4t p2b p4t p2b v1b p1b v2b p2b v3b p3b v4b p4b h1sa p5 h1ba h2sa 2 p6 h2ba ra p7 h1sb p5 p5 h1bb p6 h2sb 2 p6 p6 h2bb p5 rb p7 p7 1 or off 3 p7 1 or off 3 h1sc p5 p5 1 or off 3 p5 p5 1 or off 3 h1bc h2sc 2 p6 p6 1 or off 3 p6 p6 1 or off 3 h2bc rc p7 p7 1 or off 3 p7 p7 1 or off 3 h1sd p5 p5 1 or off 3 p5 p5 1 or off 3 h1bd p6 h2sd 2 p6 p6 1 or off 3 p6 p6 1 or off 3 h2bd p5 rd p7 p7 1 or off 3 p7 1 or off 3 p7 1 or off 3 # lines/frame (minimum) 1666 3332 1666 3332 # pixels/line (minimum) 2492 4984 1. for optimal performance of the sensor. may be clocked at a lower frequency. if clocked at a lower frequency, the frequency se lected should be a multiple of the frequency used on the a and b register. 2. h2slx follows the same pattern as h2sx for optimal speed performance, use a separate clock driver. 3. off = +5 v. note that there may be operating conditions (high temperature and/or very bright light sources) that will cause b looming from the unused c/d register into the image area.
kai ? 16050 www.onsemi.com 26 photodiode transfer timing a row of charge is transferred to the hccd on the falling edge of v1 as indicated in the p1 pattern below. using this timing sequence, the leading dummy row or line is combined with the first dark row in the hccd. the ?last line? is dependent on readout mode ? either 1666 or 3332 minimum counts required. it is important to note that, in general, the rising edge of a vertical clock (patterns p1 ? p4) should be coincident or slightly leading a falling edge at the same time interval. this is particularly true at the point where p1 returns from the high (3 rd level) state to the mid ? state when p4 transitions from the low state to the high state. figure 20. photodiode transfer timing last line l1 + dummy line p1b p2b p3b p4b pattern l2 p1t p2t p3t p4t t v t v /2 t pd t v /2 t v /2 t d t d t 3p t 3d t v t hs t v t v /2 t v t hs t v /2 t v /2 p5 p6 p7 1 2 3 4 5 6 line and pixel timing each row of charge is transferred to the output, as illustrated below , on the falling edge of h2sl (indicated as p6 pattern). the number of pixels in a row is dependent on readout mode ? either 2492 or 4984 minimum counts required. figure 21. line and pixel timing p1t p5 p6 p7 pixel n pixel 1 pixel 34 t line t v t hs t e t r t e /2 vout pattern p1b t v
kai ? 16050 www.onsemi.com 27 pixel timing detail figure 22. pixel timing detail p5 p6 p7 vout t hv t rv frame/electronic shutter timing the sub pin may be optionally clocked to provide electronic shuttering capability as shown below. the resulting photodiode integration time is defined from the falling edge of sub to the falling edge of v1 (p1 pattern). figure 23. frame/electronic shutter timing p1t/p4b p6 sub t int t frame t hd t hd t sub pattern vccd clock edge alignment figure 24. vccd clock rise time, fall time and edge alignment v vcr 90% 10% t vr t vf t v t vr t vf t v
kai ? 16050 www.onsemi.com 28 line and pixel timing ? vertical binning by 2 figure 25. line and pixel timing ? vertical binning by 2 p1t p2t p3t p4t p1b p2b p3b p4b p5 p6 p7 vout pixel n pixel 34 pixel 1 t v t v t v t hs t hs fast line dump timing the fdg pins may be optionally clocked to efficiently remove unwanted lines in the image resulting for increased frame rates at the expense of resolution. below is an example of a 2 line dump sequence followed by a normal readout line. note that the fdg timing transitions should complete prior to the beginning of v1 timing transitions as illustrated below. figure 26. fast line dump timing
kai ? 16050 www.onsemi.com 29 storage and handling table 22. storage conditions description symbol minimum maximum units notes storage temperature t st ? 55 +80 c 1 humidity rh 5 90 % 2 1. long term storage toward the maximum temperature will accelerate color filter degradation. 2. t = 25 c. excessive humidity will degrade mttf. for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com .
kai ? 16050 www.onsemi.com 30 mechanical information completed assembly figure 27. completed assembly (1 of 2) notes: 1. see ordering information for marking code. 2. no materials to interfere with clearance through package holes. 3. units: in [mm]
kai ? 16050 www.onsemi.com 31 figure 28. completed assembly (2 of 2) notes: 1. units in [mm]
kai ? 16050 www.onsemi.com 32 cover glass figure 29. cover glass notes: 1. substrate = schott d263t eco 2. dust, scratch, inclusion specification: a.) 20 m max size in zone a 3. mar coated both sides 4. spectral transmission a.) 350 ? 365 nm: t 88% b.) 365 ? 405 nm: t 94% c.) 405 ? 450 nm: t 98% d.) 450 ? 650 nm: t 99% e.) 650 ? 690 nm: t 98% f.) 690 ? 770 nm: t 94% g.) 770 ? 870 nm: t 88% 5. units: in [mm]
kai ? 16050 www.onsemi.com 33 cover glass transmission figure 30. cover glass transmission on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warrant y, representation or guarantee regarding the suitability of it s products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 kai ? 16050/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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